Summary
Imagine what you could do here. At Apple, new ideas have a way of becoming great products very quickly. Do you want to bring passion and dedication to your job? There is no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices — we continue to strengthen our commitment to leave the world better than we found it. By now the industry is accustomed to Apple taping out the SoCs for our various products at a rigorous pace. In order to achieve this, our world‑class design processes are driven by our top‑notch Physical Design engineers. Are you a classic partition PnR engineer recognised in the industry for the knowledge in standards and practices in Physical Design? Do you have a strong track record with recent successful tape‑outs in deep sub‑micron technology? As a SoC Digital Physical Design Engineer you will take part in the large‑scale SoC physical design cycle from netlist to tape‑out, including full flow of back‑end implementation and verification, always meeting schedule and design goals. Are you ready to join some of the world’s leading engineers, and help us deliver the next generation of ground‑breaking Apple products? Join Us!
Description
You will own block‑level PnR, floor‑planning, clock and power distribution. You will get involved with static timing closure using commercial tools. You will perform power and noise analysis (EM/IR‑Drop/Xtalk) as well as layout verification (DRC/LVS). You will develop and validate low‑power clock network guidelines. With a phenomenal focus you will resolve design and flow issues related to physical design, identify potential solutions, and drive execution. You understand what documentation should look like and will help with guidelines and specs.
Minimum Qualifications
* You hold an MSEE or equivalent strong experience.
* You have hands‑on experience with one of the PnR tools available today (Synopsys / Cadence) and a solid understanding of their capabilities and underlying algorithms.
* You can script and program using several of the following: Perl, TCL and Make.
Preferred Qualifications
* Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz.
* Working knowledge of Verilog is a huge plus.
* Excellent communication skills and a love for working in an open and multicultural environment.
* Familiarity with hierarchical design approach, top‑down design, and timing and physical convergence.
* In‑depth understanding of static‑timing analysis, extensive knowledge of clock/power distribution and analysis, RC extraction and correlation.
* Experience with SoC practices such as multiple voltage and clock domains, integration of mixed‑signal IPs and I/O integration.
At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.
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