We are looking for a highly experienced Digital Physical Design Engineer to support complex SoC implementation activities at both block and full-chip level.
The role focuses on end-to-end physical implementation, from early floorplanning through to final sign-off, ensuring that designs meet performance, power, and area targets while achieving full timing closure.
You will be working closely with RTL, verification, and DFT teams in a multi-disciplinary SoC environment.
-Own and execute full physical implementation flow, including floorplanning, power planning, placement, clock tree synthesis, routing, and physical optimisation
-Drive timing closure across multiple operating corners using advanced static timing analysis techniques
-Perform physical verification and sign-off activities, including DRC, LVS, and ERC checks using industry-standard tools
-Identify, analyse, and resolve design issues related to timing, signal integrity, IR drop, and electromigration
-Ensure designs meet required power, performance, and area targets during implementation and sign-off stages
-Collaborate closely with RTL, DFT, verification, and backend teams to achieve full chip closure
Support tape-out readiness and ensure high-quality deliverables for production
-10+ years of experience in digital physical design for ASIC or SoC development
-Strong hands-on experience with industry implementation tools such as Cadence Innovus and Synopsys ICC2
-Proficiency in static timing analysis tools such as PrimeTime or Tempus
-Solid experience with physical verification flows, including Calibre-based DRC and LVS sign-off
-Strong understanding of timing constraints, closure methodologies, and sign-off requirements
-Experience working with advanced technology nodes and low-power design considerations
-Ability to debug and resolve complex implementation issues across multiple domains