Join a highly innovative technology team pushing boundaries in advanced mixed-signal and digital IC development. We are searching for skilled engineers who excel in
front-end RTL
and/or
back-end physical design
, contributing to new generations of high-performance architectures in nodes such as
22FDX and advanced FinFET/FD-SOI
processes.
Whether you are a rising mid-level engineer or a seasoned leader, you will have the chance to shape subsystem architectures, influence methodologies, and drive silicon success.
Your Core Mission
Depending on your expertise, you will play a key role in:
Frontend responsibilities
* Develop and refine RTL for performance-critical digital components (DSP engines, interfaces, control blocks).
* Create micro-architectures and collaborate closely with analog/mixed-signal teams.
* Support verification and prepare design collateral including testbenches and documentation.
Backend responsibilities
* Execute and optimize physical design flows: synthesis, floorplan, CTS, place & route, STA, signoff.
* Troubleshoot timing, power, and physical integrity topics.
* Guide smooth integration into top-level mixed-signal assemblies.
What You Bring
* Solid experience in either RTL design or physical implementation — ideally both.
* Hands-on use of EDA tools from
Synopsys, Cadence or Mentor.
* Know-how in
low power design
, clock domain crossings, and hierarchical SoC concepts.
* Strong scripting skills (e.g., Python, TCL) to enhance automation and efficiency.
* Exposure to
advanced semiconductor nodes
including 22FDX or 16/12nm families.
* Knowledge of mixed-signal interaction and testability (DFT appreciated).
If you're excited about pushing digital IC boundaries and enjoy both challenge and ownership, we'd love to hear from you. Apply today — or send questions/applications directly to: -