Your mission
As a Formal Verification Engineer at LUBIS EDA, you will have a dual responsibility:
1. Consulting Services:
o Work directly with clients to verify their RTL designs and IPs.
o Create, implement, and debug Assertion IP (AIP) based on customer verification requirements.
o Develop properties, identify and report bugs, and collaborate with the client’s design team to resolve issues.
o Ensure all verification deliverables meet quality standards and project timelines.
2. Software Automation:
o Contribute to the design and development of LUBIS EDA’s in-house software tools for automating the Formal Verification process.
o Collaborate with the software development team to develop new methodologies, enhance usability, and address customer pain points.
3. Project and Client Management (Senior/Staff Engineers):
o Project Management:
+ Take ownership of formal verification projects, ensuring they are delivered on time, within scope, and to the highest quality.
* Plan project execution strategies, allocate resources, and track progress using project management tools.
* Lead technical reviews and provide mentoring to junior team members.
* Client Management:
o Serve as the primary technical point of contact for clients, ensuring their requirements are understood and met.
o Proactively manage client expectations, providing regular updates and addressing any concerns.
o Identify opportunities for additional client engagements or improvements to the verification process.
o Represent LUBIS EDA in client meetings, fostering trust and long-term relationships.
Key Responsibilities
* Analyze RTL designs, create properties, and run verification scenarios using formal tools (e.g., JasperGold, Questa Formal, Cadence IFV).
* Debug and analyze verification failures, working closely with the client’s design and verification teams.
* Automate repetitive tasks in verification workflows and contribute to toolchain improvements.
* Provide feedback from client projects to drive the roadmap for LUBIS EDA’s software solutions.
* Stay up-to-date with the latest advancements in formal verification tools, techniques, and industry trends.
* Document processes and methodologies to ensure knowledge sharing across the team.
Your profile
Must-Have Skills:
* Solid understanding of Formal Verification techniques and tools.
* Experience in verifying complex RTL designs using formal methods.
* Proficiency in SystemVerilog Assertions (SVA) and usage of Formal Engines (e.g. VCF) in the context of Formal Property Checking.
* Strong problem-solving and debugging skills.
About us
LUBIS is a fast-growing German startup redefining how the semiconductor industry works. We tackle one of its hardest challenges — ensuring complex chips work flawlessly before
they’re built.
Our mission is simple: to transform verification from a craft into a system. By structuring how teams work and automation we make chip design faster, reliable, and bug-free.
LUBIS isn’t just improving the process — we’re defining how verification is done.