In this role, you will find yourself at the core of our hardware development endeavors. As part of the memory compiler team, you will work closely with foundry, compiler vendors, and design teams, integrating new ideas and collaborating with dedicated engineers. Your efforts will directly influence the Performance Power Analysis (PPA) of end products. You will: - Drive the development of SRAM, register files, and latch arrays to enable high-performance, low-power design. - Possess a comprehensive understanding of globally available IC compilers. - Lead the SRAM compiler IP requirements for foundry, vendors, and internal IP teams. - Understand the complete design flow spectrum, including DFT and testing aspects of compiler IPs, and integrate them into our SOCs - Collaborate with logic/architecture teams to capture specifications of SRAM, register files, and latch arrays, driving their implementation. A Bachelor’s in Electrical Engineering (BSEE) is required. Significant circuit design experience. Expertise in developing memory arrays, high-performance, low-power circuit design, and register file/SRAM arrays. Proficiency in industry-standard circuit simulation, design tools, and top-level integration tools. A solid understanding of device physics and process. Masters/PhD in Electrical Engineering. SRAM design experience from schematic to layout to post-silicon analysis. Track record of successful tape-out of high-performance, low-power circuit design, particularly in SRAM and register file arrays in the latest technology nodes. Strong leadership skills, including the ability to guide multi-functional teams through failure analysis, corrective action plans, and yield bridges for successful ramp-up and mass production. Exceptional technical expertise with the ability to present complex technical topics to diverse audiences. Experience with ML-based programming algorithms. Ability to provide automation solutions for rapid and dynamic design needs.