About the Role In this role, you will be building the digital part of the SEMRON’s future chip generations. You will design, verify and optimize digital designs to meet our ambitious performance targets. What you will do: Design the digital part of SEMRON’s AI accelerator Contribute to system architecture exploration efforts Work closely with analog and software team to exchange requirements and implement them Conduct power, performance and timing analysis Develop timing constraints What you should bring in: In-depth knowledge in RTL design Experience with RTL simulation tools A good understanding in digital design trade-offs Basic knowledge on scripting (e.g. tcl, python) and systems programming (e.g. C, C++) Familiarity with low power design techniques Helpful but not required: Experience with the Chisel HDL Experience in verification Experience in mixed signal simulation Experience with RISC-V About us SEMRON develops a 3D scaled AI inference chip, incorporating GPT-3.5-like models on a square cm silicon with minimal power consumption. This revolutionary CMOS-compatible semiconductor technology enables running generative AI at the edge, making it possible for wearable tech, smartphones, and beyond. With a trend towards large foundation models, SEMRON can serve multiple markets with minimal adjustments and simplify the software stack.