About the Role In this role, you will be building the digital part of the SEMRON’s future chip generations. You will design, verify and optimize digital designs to meet our ambitious performance targets. What you will do: Design the digital part of SEMRON’s AI accelerator Contribute to system architecture exploration efforts Work closely with analog and software team to exchange requirements and implement them Conduct power, performance and timing analysis Develop timing constraints What you should bring in: In-depth knowledge in RTL design Experience with RTL simulation tools A good understanding in digital design trade-offs Basic knowledge on scripting (e.g. tcl, python) and systems programming (e.g. C, C++) Familiarity with low power design techniques Helpful but not required: Experience with the Chisel HDL Experience in verification Experience in mixed signal simulation Experience with RISC-V About us At SEMRON, we’re redefining what’s possible in AI hardware. Our core innovation lies in analog in-memory computing for deep neural network acceleration, enabling us to build compute architectures that scale vertically into the third dimension, much like NAND flash revolutionized memory. This leap in physical density allows us to deploy models with billions of parameters on chip areas as small as a few square millimeters.