Ihre Aufgaben:
* Develop verification specifications and plans for complex SoCs and IP blocks
* Lead and execute verification at module, cluster, and top-level
* Design and implement UVM-based test environments for functional, gate-level, and low-power simulations
* Develop reusable Verification IP (VIP) using the UVM framework
* Integrate reference models and VIP components into SystemVerilog and SystemC testbenches
* Develop reference models in SystemVerilog, Matlab, or Python
* Execute and analyze regression simulations and monitor coverage progress
* Debug digital modules using advanced simulation and formal verification tools
* Contribute to system-level simulations and virtual prototyping using SystemVerilog UVM and SystemC
* Understand system and IP requirements and specifications and derive corresponding test strategies
* Verify UWB-related digital designs, including protocol logic, timing behavior, and RF-related digital signal processing paths
Ihre Qualifikationen:
* Degree in Electrical Engineering, Computer Engineering, Computer Science, Physics or a related field
* Strong experience with SystemVerilog and UVM, ideally including SystemC
* Proven background in digital verification, including simulation and formal methods
* Practical experience in UWB (Ultra-Wideband) verification is mandatory
* Familiarity with SoC verification environments and EDA tools
* Knowledge of Matlab and/or Python is beneficial
* Strong analytical thinking, problem-solving skills and attention to detail
* Enjoys collaborative work with design, system and lab teams
Ihre Vorteile:
* A very renowned company
* Remote Work possible