Summary:
Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. In this role, you will be a key part of the Cellular SoC Integration team in Munich, Germany. As Frontend-STA engineer you are the focal point for constraints development as well as design- and timing analysis. Together with RTL designers, Physical designers, and other integration teams, you will work on very exciting designs and sophisticated technology nodes.
Key Qualifications:
Hands-on experience on multiple projects with constraint development, -analysis, and -debugging. Experience with industry-standard tools for STA, e.g. PrimeTime or Tempus. Good understanding of hierarchical design approaches, top-down design, timing budgeting as well as timing and physical convergence. Proficient in day-to-day usage of scripting languages (TCL, Perl, shell), Linux, and revision control systems (e.g. PerForce) Good understanding of Verilog and the ability to analyze RTL/Netlist designs Experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs, and power optimizations would be a huge plus Experience with synthesis, logic equivalence, or ECO techniques would be a plus Good communication skills and the ability to find effective technical solutions between RTL-Design and Physical-Design teams English language proficiency is required for this position
Description:
You will be responsible for constraint development, including deliveries for synthesis, PnR, and sign-off STA. You will work on partition- as well as SoC-level and verify the results post-synthesis for all STA modes. In this role, you will be the link between digital design, mixed-signal design (.lib definition), and physical design. Your responsibility is to achieve sign-off quality of timing constraints, based on stakeholder requirements. Further, you will closely collaborate with digital designers to understand the design intent and its clock structure to optimize power, performance, and area. With CAD and PD teams you will continuously improve development flows.
Additional Requirements: