Job Description
YOU…
* verify mixed-signal designs on block and system level resting upon formal and functional verification
* interpret product requirements to create the verification concept and the product verification specification
* perform random-constraint testbenches according to the state of the art
* create assertions to prove the design using formal methods
* work in collaboration with lab and test engineers, designers, system architects, and verification engineers across multiple sites
Qualifications
YOU…
* have completed engineering degree in electrical engineering, computer science or similar studies
* already have practical experience in the field of digital functional verification and common safety standards
* have extensive programming skills in coding in System Verilog and System Verilog assertions
* have good knowledge of UVM methodology and Specman - e language, scripting languages like Python or Perl and ability to interpret RTL and Gatelevel code
* have good communication skills in English
We value diversity and therefore welcome all applications - regardless of gender, nationality, ethnic and social origin, religion/belief, disability, age and sexual orientation and identity.
Severely disabled persons will be given preferential consideration if they are equally qualified.
Do you have any questions?
Then contact me: Özlem Mumin (Tel.: +49 89 255552-331)
Or apply now using our online application form.
Additional Information
* Talent Management - we develop your career
* Work life balance - flexible working hours and mobile working possible
* Fit and relaxed – with EGYM Wellpass
* Enjoy biking – always on tour with bike leasing
* Green Mobility - with us you can travel at a reduced rate
...in addition we offer a permanent employment contract, corporate benefits and team events.