Verification Engineer
(m/f/d)
Employment with Hays Professional Solutions GmbH Neuried Start date: asap Reference number: 821993/1
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About the company
1. Location: Remote (70-90%)
Responsibilities
2. Develop and implement verification strategies for complex SoC and ASIC designs
3. Create and maintain testbenches for functional verification
4. Apply verification methodologies such as UVM, SystemVerilog, or VHDL
5. Analyze and debug design issues, collaborating closely with design and software teams
6. Conduct simulations and generate verification reports
7. Support the development of verification automation and scripting
8. Perform validation and testing on FPGA and hardware prototypes
Profile
9. Solid experience in multiple project verification sign-off (both IP and SoC verification)
10. Specman E language and UVM methodology expertise
11. Hands on experience with SystemVerilog assertions
12. Understanding of ARM-AMBA protocols, Verilog constructs to debug RTL issues und C++ constructs to debug tlm models
13. Working experience with Cadence simulation/regression tools (Xcelium, Specman-elite, SimVision, vManager)
14. Experience on requirement-based verification for ISO/safety projects
15. Experience with Graphics processing IPs, experience with Formal Property checking and other automated tools
16. For initial setup and kick-off it is desirable to visit SNEU office
17. For reviews and critical deliverables, it might be required to visit SNEU in future
Benefits
18. 30 days leave per year
19. A city with a high quality of life that perfectly embraces both modern and traditional values
20. A highly motivated team and an open way of communication
21. Remote work possible