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Senior dft engineer

Frankfurt am Main
Ciena Limited, German Branch
Ingenieur
Inserat online seit: 5 August
Beschreibung

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

How You Will Contribute:
As a Senior DFT Design Engineer you will be responsible for defining and implementing DFT features for SOCs such as scan and BIST as well as coding and verification of DFT timing constraints. Automatic test pattern generation (ATPG) and verification is also part of the job scope. You will contribute to chip level DFT architecture, align schedules and deliverables and support the test teams in test program development. In your role you will report to the Backend Design Manager in Braunschweig, Germany but you will also work as a part of the Ciena global ASIC design team. Your role will involve the following key functions:

1. Insert scan test, MBIST and other test features on netlist level and RTL
2. Work with RTL designers on improving RTL for test coverage
3. Work with analog IP teams to include their IP in digital test where possible
4. Work with EDA vendors to deploy new tool features and address tool issues
5. Execute Automatic Test Pattern Generation (ATPG) and conduct pattern re-simulation and gate level simulation
6. Implement test clock architectures and provide timing constraints for STA
7. Implement DFT automation and include the scripts in the central design flow
8. Implement boundary scan IEEE1149.1 and other standards

The Must Haves:

9. Minimum of Bachelors degree in Engineering or Science coupled with 5+ years of industry experience in ASIC digital design and Design for Test (DFT)
10. Proven experience with DFT and digital simulation tools from one of the major EDA vendors such as Siemens, Cadence, Mentor
11. Experience in applying IEEE Test Standards (1149.1, 1500, 1687 and 1838) for SOCs and chiplets
12. Excellent programming skills especially in TCL to automate tasks
13. Experience in collaboration with test teams worldwide on ATE test program development
14. Sound command of written and spoken English

Assets:

15. Self-motivated, ability to work in a multi-site, international teams
16. Own assignments with full accountability, remain engaged, be proactive and positive while solving very challenging problems.
17. Willing to conduct occasional international business travel as well as regular travel to Braunschweig office for team meetings

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At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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