Job Description
As a Graduate Digital Backend Engineer, you will participate in the end‑to‑end physical implementation of complex SoC and mix-signal designs. You will work within an experienced backend team and learn how to transform RTL code into a tape‑out‑quality GDSII database using the Cadence digital implementation tool suite. The role spans the complete backend flow including synthesis, floorplanning, power planning, place & route, timing closure, physical verification, and sign‑off.
You will receive structured coaching, access to internal training material, and the opportunity to work on real production designs while gradually taking ownership of specific blocks.
1. RTL Synthesis (Cadence Genus)
1. Run logic synthesis and generate optimized netlists according to timing, area, and power constraints.
2. Perform constraint development and validation (SDC).
3. Analyze synthesis reports: timing, area, power, QoR, and identify optimization opportunities.
4. Collaborate with RTL and verification teams to resolve structural issues.
2. Floorplanning & Power Planning (Cadence Innovus)
5. Assist in creating initial chip and block floorplans, including die/core sizing, aspect ratio, macro placement, and I/O planning.
6. Support power grid (PG) design, power rail planning, and IR‑drop‑aware placement.
7. Ensure integration of physical IP (memories, analog blocks, hard macros).
3. Placement, Clock Tree Synthesis & Routing
8. Run placement, CTS, and detailed routing using Cadence Innovus.
9. Perform optimization iterations for timing, congestion, and power.
10. Implement design‑for‑manufacturability (DFM) and power‑intent (UPF) guidelines.
11. Ensure correctness of CTS: skew, slew, balancing, and power efficiency.
4. Static Timing Analysis (Cadence Tempus)
12. Analyze and resolve setup/hold violations across multiple modes and corners.
13. Work with multi‑corner, multi‑mode (MCMM) analysis environments.
14. Debug timing paths, parasitics, and cross‑talk using Cadence sign‑off flows.
5. Power & IR‑Drop Analysis (Cadence Voltus)
15. Prepare power models and scenarios for dynamic and static IR‑drop analysis.
16. Perform EM/IR validation and support PDN optimization.
17. Interpret results and propose improvements in PG design or standard‑cell usage.
6. Physical Verification (Mentor Calibre)
18. Run DRC, LVS, and ERC checks on full layouts.
19. Debug physical verification violations and collaborate with layout engineers.
20. Ensure the design meets manufacturing requirements and PDK guidelines.
7. Sign‑off, ECO Handling & Final GDSII Output
21. Execute ECO cycles using Cadence Innovus/Genus ECO flows.
22. Validate timing, power, signal integrity, and physical verification after ECOs.
23. Prepare the final, tape‑out‑ready GDSII database.
24. Support documentation and sign‑off reviews for tape‑out
Qualifications
25. Master’s or Bachelor’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
26. Solid understanding of CMOS fundamentals, digital design, and VLSI basics.
27. Familiarity with Verilog/VHDL, SDC constraints, and Unix/Linux workflows.
28. Basic exposure to scripting languages (TCL, Python, or Perl).
29. Strong analytical thinking and problem‑solving skills.
30. Proactive, collaborative, and eager to learn.
Nice‑to‑Have Skills
31. Knowledge of RTL synthesis or P\&R concepts through academic projects or internships.
32. Understanding of timing analysis, STA concepts, or physical verification.
33. Experience with any EDA tool (Cadence, Synopsys, Mentor).
What We Offer
34. Structured onboarding and mentorship by experienced Senior Engineers.
35. Hands‑on work on real production ASICs/SoCs.
36. Access to industry‑standard EDA tools (Cadence Genus/Innovus/PrimeTime).
37. Career growth path toward Physical Design Engineer or Implementation Lead.
38. Opportunity to contribute to tape‑outs across multiple technology nodes.