We are looking for a dedicated student who loves challenges, brings the ability to learn and wants to become a part of our multi-faceted team. Your responsibilities will include: - In this role you will work with design team to understand partition architecture and participate in driving physical aspects in an early design cycle. - You will participate in netlist to GDS2 implementation work, be it in Place and Route, timing, physical & electrical verification, or signoff. - You will be exposed to design and flow issues related to physical implementation, identify potential solutions and help drive execution. Currently enrolled in a Bachelor/Master/PhD Degree program in Electrical Engineering or Computer Science or equivalent. Excellent communication and interpersonal skills, combined with the ability to collaborate. Proficiency in English required. Good knowledge of digital logic gates, clocking and state elements Basic scripting skills in Python, Perl and TCL Familiarity with the physical design process and interested in areas like Synthesis, Place and Route (PnR) and Static Timing Analysis (STA) Ability to work in a dynamic and fast-paced environment, adapting to changing project requirements and priorities