Duisburg or Munich as working locations Task Physical design of RF/Analog SiGe BiCMOS circuit modules with CadenceVirtuoso XL in strong cooperation with design engineering team Block level layout through full verification flow (DRC, LVS) with Cadence Assura/PVS DRC tools Floor-planning in collaboration with RF IC design and RF system team Scripting of tasks (e.g. Skill, Python) Tape out procedure Qualification Several years of custom RF/analog layout experience with extensive knowledge of SiGe BiCMOS processes Detail knowledge of layout techniques for device matching, parasitic reduction, RF shielding and optimal high frequency routing Deep understanding of the full design flow from schematic to GDSII, including verification (DRC, LVS) and process design kits Good communication skills - Completed studies of electrical engineering or similar Fluent German and English language (C1-Level)