Looking for a telecommunication/networking expert to help us implement the inference of AI models on programmable network nodes in different 5G/6G network settings: The workload for the target AI application will need to be distributed on a group of networking nodes (e.g., switches, SmartNICs, base stations), having heterogeneous hardware architecture.
Tasks
1. Define the industrial constraints on B5G/6G KPIs, such as latency, resource footprint, bandwidth, and for different types of evolutionized networks related to RAN, WAN, LAN, MEC, etc.
2. Help to realize the customized implementation of AI models on a distributed group of heterogeneous hardware of telecommunication devices (e.g., switches, SmartNICs, base stations).
3. Adjust aforementioned customized implementations for different networking protocols (e.g., IPv6, Ethernet, TSN, HTTP, etc).
4. Help to design scalable scheduling, orchestration, and dynamic resource allocation algorithms, required to integrate aforementioned distributed AI implementations in various network settings.
5. Lead the technical validation and prototyping with early adopters.
6. Collaborate on grant writing, product roadmap, and tech strategy.
7. Hire and mentor future engineers and researchers as the team grows.
Requirements
1. Based in Germany, with a valid Niederlassungserlaubnis or German citizenship.
2. A Master's or PhD in Computer Science, Electrical Engineering, or related fields in telecommunication and networking.
3. Proven ability to build systems end-to-end: from prototype to deployable demo.
4. Experienced in energy efficiency, sustainability, high-throughput, and other impactful design goals.
5. Fluent in English; German is a bonus.
6. Strong background in Networking / Telecommunication with focus on:
7. Understanding of the 5G/6G stack, from radio access to packet processing.
8. Experience in distributed computing frameworks and edge/cloud orchestration.
9. A basic background in the following fields:
Machine Learning:
* Structure of DNNs, LLMs, or other AI models for embedded / edge devices.
* Quantization, pruning, knowledge distillation, or other optimization techniques for ML.
Hardware Design:
* Design and synthesis of AI accelerators for FPGAs or custom ASICs.
* Circuit-level optimization, High-Level Synthesis (HLS), or RTL design experience.
Benefits
Non-paid job at the moment, equity share at the time of founding the company is considered.
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