Responsibilities develop SystemVerilog code to implement the required digital functionality adapt and enhance existing IP modules to support new features and requirements set up and execute logic synthesis including constraint management perform implementation verification using Spyglass and Logic Equivalence Checking (LEC) conduct power simulations and analyze results Prepare comprehensive design documentation. Qualifications have completed degree in Electrical Engineering Computer Science Physics or similar studies have proven experience in RTL design and verification (SystemVerilog VHDL) have a strong background in logic synthesis timing analysis and power simulation have experience with industry-standard tools : Spyglass DesignCompiler LEC Xcelium ATPG have good communication skills in English We value diversity and therefore welcome all applications - regardless of gender nationality ethnic and social origin religion / belief disability age and sexual orientation and identity. Severely disabled persons will be given preferential consideration if they are equally qualified. Do you have any questions Then contact me : Özlem Mumin (Tel. : -331) Or apply now using our online application form. Additional Information Talent Management - we develop your career Work life balance - flexible working hours and mobile working possible Fit and relaxed with EGYM Wellpass Enjoy biking always on tour with bike leasing Green Mobility - with us you can travel at a reduced rate ...in addition we offer a permanent employment contract corporate benefits and team events. Remote Work : No Employment Type : Full-time Vacancy : 1 #J-18808-Ljbffr