<p><strong>Senior RTL Digital Design Engineer</strong></p><p>Duration - 10 months</p><p><br></p><p>Job Description:</p><p>We are seeking a skilled Front-End RTL Design Engineer with 10+ years of experience in digital design and SoC development. The role involves RTL design, subsystem/SoC integration, and ensuring high-quality design implementation through rigorous verification and sign-off checks.</p><p><br></p><p>Key Responsibilities:</p><p>• Perform subsystem and full SoC integration, ensuring interface and architectural consistency</p><p>• Execute and analyze Lint, CDC, and RDC checks to ensure robust design quality</p><p>• Develop RTL for complex digital blocks and subsystems</p><p>• Support synthesis flows and optimize designs for timing, area, and power</p><p>• Participate in simulation, debugging, and functional verification activities</p><p>• Collaborate closely with verification teams with working knowledge of UVM-based methodologies</p><p>• Contribute to design reviews, architecture discussions, and quality sign-off processes</p><p><br></p><p>Requirements:</p><p>• 10+ years of experience in RTL design and SoC/subsystem integration</p><p>• Strong knowledge of digital design fundamentals and micro-architecture</p><p>• Proficiency in synthesis tools (e.g., Synopsys Design Compiler or Cadence Genus)</p><p>• Hands-on experience with Lint, CDC, and RDC analysis and closure</p><p>• Solid understanding of simulation and digital verification concepts, including UVM</p><p>• Good scripting skills (TCL/Python) for automation</p><p><br></p><p>Nice to Have:</p><p>• Experience with SoC integration using Magillem tools (very nice to have)</p><p>• Interest or experience in applying AI/LLMs (e.g., Claude, Opus) to improve design flows, productivity, and methodology innovation (very nice to have)</p><p><br></p>