Description Change the world. Love your job. As an Analog Layout Intern, you will get hands-on experience in transistor-level layout design for analog and mixed-signal integrated circuits. You will work closely with senior layout and circuit design engineers, learning industry-standard practices and contributing to real IC development projects. Your role includes device matching, parasitic-aware layout, and verification through design rule (DRC), layout vs schematic (LVS) and parasitic extraction (PEX) to ensure high-performance and manufacturable designs. At the end you will have more detailed view how everything gets combined from a single transistor to complete IC design that is ready for production. Qualifications Minimum requirements: Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field Available for a 6 months internship, preferred start in 2026 Preferred qualifications: Strong understanding of CMOS devices, analog circuit basics, and IC fabrication concepts Familiarity with Cadence Virtuoso Knowledge of DRC, LVS and PEX verification flow Good understanding of matching techniques, shielding, guard rings, and symmetry in layout Strong attention to detail, problem-solving skills and eagerness to learn Our offer for you: Benefit from an attractive compensation Join an international work environment where your ideas count and where you can thrive in a diverse culture Explore a world of opportunities for your personal and professional development Put your talent to work with us as a Layout Engineering Intern! Texas Instruments will not sponsor job applicants for visas or work authorization for this position