About the Role In this role you are responsible for system level and integration verification of the designs, as they are produced by the RTL design team. You will also have to provide feedback during the architecture exploration process for future generation designs. You will work on SOC level designs, within a multi-power domain, and will be responsible for building our verification architecture. What you will do: Verification of low power, multi clock domain designs Work on advanced technology nodes Help RTL designers with module level functional verification Verification of SOC level design Develop the verification infrastructure What you should bring in: Willingness to learn new, potentially unconventional, technologies/techniques Experience in verification of multi clock domain designs Some experience in working with mixed signal systems Experience developing the verification infrastructure for SOC designs Experience with UVM Advanced level in Python & GIT Helpful but not required: Experience with the Chisel hardware design language Experience in working with designs beyond the standard cell libraries About us SEMRON develops a 3D scaled AI inference chip, incorporating GPT-3.5-like models on a square cm silicon with minimal power consumption. This revolutionary CMOS-compatible semiconductor technology enables running generative AI at the edge, making it possible for wearable tech, smartphones, and beyond. With a trend towards large foundation models, SEMRON can serve multiple markets with minimal adjustments and simplify the software stack.