Your tasks
* Physical design of RF/Analog SiGe BiCMOS circuit modules with Cadence Virtuoso XL in strong cooperation with design engineering team
* Block level layout through full verification flow (DRC, LVS) with Cadence Assura/PVS DRC tools
* Floor-planning in collaboration with RF IC design and RF system team
* Scripting of tasks (e.g. Skill, Python)
* Tape out procedure
Your qualifications
* Bachelor's or Master's degree in Electrical Engineering or a comparable field of study
* Several years of custom RF/analog layout experience with extensive knowledge of SiGe BiCMOS processes
* In detail knowledge of layout techniques for device matching, parasitic reduction, RF shielding and optimal high frequency routing
* Deep understanding of the full design flow from schematic to GDSII, including verification (DRC, LVS) and process design kits
* Ability to think and communicate at different levels of abstraction
* Good communication skills in English and German
Interested?
We are looking forward to receiving your application! Ideally, you should apply online with the reference number. If you have any questions, please feel free to contact your recruiting contact via LinkedIn or XING.
Equal opportunities are important to us. We are looking forward to receiving your application regardless of gender, nationality, ethnic and social origin, religion, ideology, disability, age as well as sexual orientation and identity.
Reference number: 13025
Recruiting contact: Bettina Bauer