Senior Design Verification Leader (Director / Sr. Manager Level)
Years of Experience:
* 10–15+ years in semiconductor industry with a strong background in SoC and IP Design Verification.
Technical Expertise:
* Deep expertise in design verification methodologies including UVM/OVM, constrained-random verification, coverage-driven verification, and assertion-based verification.
* Solid working knowledge of SystemVerilog, Verilog, SVA, and verification planning & closure strategies.
* Experience with simulation and formal verification flows; familiarity with tools such as VCS, Questa, Incisive, and optionally JasperGold, 0in, or other formal tools.
* Strong understanding of interfaces/protocols like PCIe, MIPI, USB, DDR, SATA, UFS, etc.
* Background in VIP (Verification IP) development is a plus.
Leadership & Program Management:
* Proven experience in building and leading multi-site verification teams (20+ engineers).
* Responsible for project planning, execution, milestone tracking, and closure for IP and SoC verification programs.
* Ability to define and enforce best practices in DV methodology, tool flow, and infrastructure.
* Comfortable managing cross-functional collaboration with design, architecture, firmware, and validation teams.
Business and Organizational Impact:
* Demonstrated experience in interfacing with clients, internal stakeholders, and executive management.
* Ability to drive client confidence and technical credibility in strategic engagements.
* Experience with pre-sales support, proposal creation (RFI/RFP/RFQ), and CoE/ODC setup is highly valued.
Soft Skills:
* Excellent communication, mentoring, and stakeholder management skills.
* Strategic thinker with an ability to scale teams and processes aligned with business growth.
* Proven track record of technical and organizational leadership in fast-paced environments.
Location Flexibility:
* Open to global collaboration and management of distributed teams.
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