Design Verification Team Lead
ASIC/SoC | Verification & Validation | SystemVerilog | UVM | Synopsys | Cadence
Do you want to lead the verification of next-generation semiconductor designs?
We are looking for a
Design Verification Team Lead
to manage verification projects for advanced
ASIC and SoC systems
. In this leadership role, you'll guide a team of engineers in ensuring functional correctness, performance, and reliability before tape-out.
What you'll do:
* Lead a team of
design verification engineers
working on ASIC/SoC projects.
* Define verification strategy, coverage plans, and project milestones.
* Oversee development of
UVM/SystemVerilog testbenches
and manage regression testing.
* Collaborate with design, architecture, and validation teams to debug and resolve design issues.
* Mentor junior engineers and ensure high-quality deliverables within timelines.
What you bring:
* 7+ years of experience
in ASIC/SoC verification, with at least
2+ years in a lead/mentorship role
.
* Strong expertise in
SystemVerilog, UVM, and coverage-driven verification
.
* Hands-on experience with
Synopsys VCS, Cadence Xcelium, or Mentor Questa
.
* Good understanding of
RTL design (Verilog/VHDL)
and EDA workflows.
* Strong leadership, communication, and organizational skills.
Onsite, Full-time – Eindhoven, Netherlands
Be part of Europe's "Brainport" hub, working on
world-class semiconductor innovations
.
Apply today and lead a team building the future of digital design.